1. Technical Field of the Invention
This invention relates to integrated circuits, and more particularly to an electrically programmable antifuse with improved manufacturability.
2. Prior Arts
Antifuse is a nonvolatile switching device used in semiconductor integrated circuits. It has been extensively used in Field Programmable Gate Arrays (FPGAs) and Programmable Read-Only Memorys (PROMs). A typical antifuse comprises a bottom electrode, an insulating antifuse layer and a top electrode. The bottom electrode provides a bottom routing channel while the top electrode provides a top routing channel. Separated from the bottom electrode by the antifuse layer, the top electrode of an unprogrammed antifuse has no electrical connection with the bottom electrode. Passage of a current sufficiently large through an antifuse can cause electrical connection between two electrodes. An antifuse is the basic unit in an FPGA chip to perform the switching function between logic modules.
In an FPGA or PROM chip, there are millions of antifuses. They are all expected to have a similar behavior. Excessive leakage in a single unprogrammed antifuse could be detrimental to the functionality of a whole chip. To ensure a high chip yield, the antifuse layer is required to have a low defect density. Because of its uniqueness, antifuse needs to fulfill more stringent defect density requirements than other conventional IC""s.
Defects could be intrinsic or extrinsic. Intrinsic defects are the defects inherent in the antifuse layer. Extrinsic defects are introduced during manufacturing process. Intrinsic defects can be addressed only by a careful selection of antifuse material. Extrinsic defects, on the other hand, can be reduced by optimizing antifuse structure and/or improving manufacturing steps. Numerous prior arts have proposed antifuse structures to improve manufacturability. But during manufacturing process, they all introduce extrinsic defects to the antifuse layer one way or the other.
U.S. Pat. No. 4,914,055 issued to Gordon et al. on Apr. 3, 1990 described a process to make an antifuse structure by depositing a bottom layer of TiW 10, a layer of amorphous silicon 12, and a top layer of TiW 14 on substrate 18. As is illustrated in FIG. 1A, amorphous silicon layer 12 is deposited in an antifuse via 20, formed in a field oxide layer 16. FIG. 1B illustrates another antifuse structure described by U.S. Pat. No. 5,196,724 issued to Gordon et al. on Mar. 23, 1993. According to this invention, amorphous silicon layer 22 is first deposited on the bottom electrode 10, then the field oxide 16 is deposited and an antifuse via is formed therein. The top electrode 14 is deposited and patterned thereafter in the antifuse via 20. In this antifuse structure, amorphous silicon layer 12 is planar. Hawley et al. described an antifuse structure in U.S. Pat. No. 5,308,795 issued May 3, 1994. As is illustrated in FIG. 1C, the bottom electrode 10 is formed first. Then the field oxide 16 is deposited over the bottom electrode 10 and a via 20 is etched therethrough. Then a planarized W plug 24 is formed by means such as Chemical Mechanical Polishing (CMP). This is followed by the formation of antifuse layer 12 and the top electrode 14.
One common problem with these inventions is that the first interface 15 between bottom electrode and antifuse layer and/or the second interface 17 between antifuse layer and top electrode are subjected to harmful processing environment during the antifuse manufacturing. Here, the first interface 15 refers to the common area shared by the bottom electrode 10 and the antifuse layer 22; the second interface 17 refers to the common area shared by the antifuse layer 22 and the top electrode 14. Photoresist, etching medium, CMP brush or even xe2x80x9cdirtyxe2x80x9d air are representative of harmful processing environment. Particularly, pattern-transferring process, e.g. photolithography, can introduce foreign particle and/or cause severe surface damage. For example, masking of the field oxide 16 can leave residue photoresist in the antifuse via 20 in FIGS. 1A and 1B. In the meantime, etching of the field oxide 16 will cause a roughened surface of the bottom electrode 10 in FIG. 1A and a nonuniform antifuse layer 12 in FIG. 1B. CMP brush can also cause scratch on the W plug 24 in FIG. 1C. Accordingly, the breakdown voltage of the antifuse layer 12 is not well under control. As a result, yield of the integrated circuit using these antifuse structures is questionable.
In order to overcome the foregoing disadvantages of prior art antifuses, a new antifuse structure is disclosed in the present invention. According to the present invention, the bottom electrode and the antifuse layer are not subjected to harmful processing environment during the antifuse manufacturing.
It is a principle object of the present invention to provide an antifuse structure with an improved manufacturability.
It is a further object of the present invention to provide an antifuse structure with an improved yield.
It is a further object of the present invention to provide an antifuse structure with a repeatable and controllable breakdown voltage.
It is a further object of the present invention to prevent the first interface between the bottom electrode and the antifuse layer from being exposed to harmful processing environment.
It is a further object of the present invention to prevent the second interface between the antifuse layer and the top electrode from being exposed to harmful processing environment.
In accordance with these and other objects of the invention, a new antifuse structure is described in the following detailed description of the preferred embodiments which are illustrated in various drawing figures.
The present invention provides an antifuse structure with an improved manufacturability. According to the present invention, the bottom electrode, the antifuse layer and the top buffer layer are formed successively in a friendly manufacturing environment. Here, a friendly manufacturing environment refers to a manufacturing environment without photoresist, etching ambient, CMP brush and slurry, etc. In one word, a friendly manufacturing environment would not introduce defects to wafer surface. The absence of masking, etching or planarizing eliminates any possibility of foreign particle introduction and damage to the exposed surface during manufacturing. Moreover, this forming step can be performed in a cluster tool. In a cluster tool the wafers are transferred in vacuum or clean air and therefore results in no foreign particle introduction. Hence, the bottom electrode and the antifuse layer are not subjected to harmful processing environment. In other words, the bottom electrode and the antifuse layer are formed in a friendly manufacturing environment. The present invention eliminates any possibility to introduce defects during manufacturing. The only possible cause of premature breakdown is from the intrinsic defects of the antifuse layer. Compared with prior arts, this antifuse structure has less defects and therefore an improved manufacturability.